A Hardware Spinal Decoder

Frank J Cangialosi, Yanif Ahmad, Magdalena Balazinska, Ugur Cetintemel, Mitch Cherniack, Jeong-Hyon Hwang, Wolfgang Lindner, Anurag S Maskey, Alexander Rasin, Esther Ryvkina, Nesime Tatbul, Ying Xing, Stan Zdonik
International Conference on System Sciences, Maui, HI, January 1998

Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel "alphabeta" incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters.

We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.

test

by boneless

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Bibtex Entry:

@inproceedings{cangialosi1998hardware,
   author =       "Frank J Cangialosi and Yanif Ahmad and Magdalena Balazinska and Ugur Cetintemel and Mitch Cherniack and Jeong-Hyon Hwang and Wolfgang Lindner and Anurag S Maskey and Alexander Rasin and Esther Ryvkina and Nesime Tatbul and Ying Xing and Stan Zdonik",
   title =        "{A Hardware Spinal Decoder}",
   booktitle =    {International Conference on System Sciences},
   year =         {1998},
   month =        {January},
   address =      {Maui, HI}
}